/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Eep_Cfg.h                                                                                 *
 *  \brief    This file contains generated pre compile configuration file for                           *
 *            EEP MCAL driver                                                                           *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date                 <th>Version                                                             *
 * <tr><td>2025-03-25 19:03:22  <td>1.0.0 R                                                             *
 * </table>                                                                                             *
 *******************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif

/********************************************************************************************************
 *                                      Include header files                                            *
 *******************************************************************************************************/
#include "Eep.h"
#include "Mcal.h"
#include "regs_base.h"

/********************************************************************************************************
 *                                  Extern Function Declarations                                        *
 *******************************************************************************************************/

/********************************************************************************************************
 *                                  Const Variable Declarations                                        *
 *******************************************************************************************************/

#define EEP_START_SEC_CONST_UNSPECIFIED
#include "Eep_MemMap.h"

static const Mram_RdBufferCfgType Eep_Controller0ReadBufferConfigs[] = {
    {
        .channelId = 0u,
        .masterId = MRAM_RDBUFFER_IGNOR_IDENT,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 1u,
        .masterId = MRAM_RDBUFFER_IGNOR_IDENT,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 2u,
        .masterId = MRAM_RDBUFFER_IGNOR_IDENT,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 3u,
        .masterId = MRAM_RDBUFFER_IGNOR_IDENT,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 4u,
        .masterId = MRAM_RDBUFFER_IGNOR_IDENT,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
};

static const Mram_RdBufferCfgType Eep_Controller1ReadBufferConfigs[] = {
    {
        .channelId = 0u,
        .masterId = MRAM_RDBUFFER_IGNOR_IDENT,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 1u,
        .masterId = MRAM_RDBUFFER_IGNOR_IDENT,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 2u,
        .masterId = MRAM_RDBUFFER_IGNOR_IDENT,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 3u,
        .masterId = MRAM_RDBUFFER_IGNOR_IDENT,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 4u,
        .masterId = MRAM_RDBUFFER_IGNOR_IDENT,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
};

static const Mram_RdBufferCfgType Eep_Controller2ReadBufferConfigs[] = {
    {
        .channelId = 0u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 1u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 2u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 3u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 4u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
};

static const Mram_RdBufferCfgType Eep_Controller3ReadBufferConfigs[] = {
    {
        .channelId = 0u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 1u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 2u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 3u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 4u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
};

static const Mram_RdBufferCfgType Eep_Controller4ReadBufferConfigs[] = {
    {
        .channelId = 0u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 1u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 2u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 3u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
    {
        .channelId = 4u,
        .masterId = 0u,
        .arid = MRAM_RDBUFFER_IGNOR_IDENT,
        .enable = TRUE
    },
};


const Eep_ConfigType  Eep_ConfigData =
{
    .initConfig =
    {
        .defaultMode = MEMIF_MODE_SLOW,
        .fastReadBlockSize = 4096,
        .fastWriteBlockSize = 1024,
        .normalReadBlockSize = 0,
        .normalWriteBlockSize = 0,
        .blockConfig = {
            {
                .baseAddress = 16777216u,
                .size = 524288u,
                .jobEndNotification = NULL_PTR,
                .jobErrorNotification = NULL_PTR,
                .priority = 1u
            },
            {
                .baseAddress = 8388608u,
                .size = 8388608u,
                .jobEndNotification = NULL_PTR,
                .jobErrorNotification = NULL_PTR,
                .priority = 0u
            }
        },
    },
    .controllerConfig =
    {
        {
            .deviceId = 0U,
            .hostConfig =
            {
                .config = {
                    .apbBase = APB_MRAM1_BASE,
#ifdef ARCH_armv8_r
                    .axiRdBase = MRAM1_F_BASE,
                    .axiWrBase = MRAM1_M_BASE,
#else
                    .axiRdBase = MRAM1_F_BASE,
                    .axiWrBase = MRAM1_F_BASE,
#endif
                    .irq = 0u, /* The interrupt need to be enable at the external upper layer */
                    .initialMode = MRAM_INIT_SW_AUOTO_WAKEUP,
                    .interleaveDis = FALSE,
                },
                .aclkHz = 300000000U,
                .tmcClkHz = 50000000U,
                .wrIntervalUs = 0U,
                .wrBufferEnable = FALSE
            },
            .eventNotification = NULL_PTR,
            .rdBufferConfigs = Eep_Controller0ReadBufferConfigs,
            .rdBufferConfigsNum = 5u,
            .semagID = 0xFFu,
        },
        {
            .deviceId = 1U,
            .hostConfig =
            {
                .config = {
                    .apbBase = APB_MRAM2_BASE,
#ifdef ARCH_armv8_r
                    .axiRdBase = MRAM2_F_BASE,
                    .axiWrBase = MRAM2_M_BASE,
#else
                    .axiRdBase = MRAM2_F_BASE,
                    .axiWrBase = MRAM2_F_BASE,
#endif
                    .irq = 0u, /* The interrupt need to be enable at the external upper layer */
                    .initialMode = MRAM_INIT_SW_AUOTO_WAKEUP,
                    .interleaveDis = FALSE,
                },
                .aclkHz = 300000000U,
                .tmcClkHz = 50000000U,
                .wrIntervalUs = 0U,
                .wrBufferEnable = FALSE
            },
            .eventNotification = NULL_PTR,
            .rdBufferConfigs = Eep_Controller1ReadBufferConfigs,
            .rdBufferConfigsNum = 5u,
            .semagID = 0xFFu,
        },
        {
            .deviceId = 2U,
            .hostConfig =
            {
                .config = {
                    .apbBase = APB_MRAM3_BASE,
#ifdef ARCH_armv8_r
                    .axiRdBase = MRAM3_F_BASE,
                    .axiWrBase = MRAM3_M_BASE,
#else
                    .axiRdBase = MRAM3_F_BASE,
                    .axiWrBase = MRAM3_F_BASE,
#endif
                    .irq = 0u, /* The interrupt need to be enable at the external upper layer */
                    .initialMode = MRAM_INIT_SW_AUOTO_WAKEUP,
                    .interleaveDis = FALSE,
                },
                .aclkHz = 300000000U,
                .tmcClkHz = 50000000U,
                .wrIntervalUs = 0U,
                .wrBufferEnable = FALSE
            },
            .eventNotification = NULL_PTR,
            .rdBufferConfigs = Eep_Controller2ReadBufferConfigs,
            .rdBufferConfigsNum = 5u,
            .semagID = 0xFFu,
        },
        {
            .deviceId = 3U,
            .hostConfig =
            {
                .config = {
                    .apbBase = APB_MRAM4_BASE,
#ifdef ARCH_armv8_r
                    .axiRdBase = MRAM4_F_BASE,
                    .axiWrBase = MRAM4_M_BASE,
#else
                    .axiRdBase = MRAM4_F_BASE,
                    .axiWrBase = MRAM4_F_BASE,
#endif
                    .irq = 0u, /* The interrupt need to be enable at the external upper layer */
                    .initialMode = MRAM_INIT_SW_AUOTO_WAKEUP,
                    .interleaveDis = FALSE,
                },
                .aclkHz = 300000000U,
                .tmcClkHz = 50000000U,
                .wrIntervalUs = 0U,
                .wrBufferEnable = FALSE
            },
            .eventNotification = NULL_PTR,
            .rdBufferConfigs = Eep_Controller3ReadBufferConfigs,
            .rdBufferConfigsNum = 5u,
            .semagID = 0xFFu,
        },
        {
            .deviceId = 4U,
            .hostConfig =
            {
                .config = {
                    .apbBase = APB_MRAM5_BASE,
#ifdef ARCH_armv8_r
                    .axiRdBase = MRAM5_F_BASE,
                    .axiWrBase = MRAM5_M_BASE,
#else
                    .axiRdBase = MRAM5_F_BASE,
                    .axiWrBase = MRAM5_F_BASE,
#endif
                    .irq = 0u, /* The interrupt need to be enable at the external upper layer */
                    .initialMode = MRAM_INIT_SW_AUOTO_WAKEUP,
                    .interleaveDis = FALSE,
                },
                .aclkHz = 200000000U,
                .tmcClkHz = 50000000U,
                .wrIntervalUs = 0U,
                .wrBufferEnable = FALSE
            },
            .eventNotification = NULL_PTR,
            .rdBufferConfigs = Eep_Controller4ReadBufferConfigs,
            .rdBufferConfigsNum = 5u,
            .semagID = 0xFFu,
        },
    }
};

#define EEP_STOP_SEC_CONST_UNSPECIFIED
#include "Eep_MemMap.h"

#ifdef __cplusplus
}
#endif
/* End of file */
